Hash function for hardware implementations
US8359346B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 5, 2009 |
| Grant date | Jan 22, 2013 |
| Priority date | — |
| Expiry date | Nov 23, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2209/80
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A logic block is presented that generates avalanche criterion hash values using minimal logic. The logic block includes a first exclusive-OR function, a second exclusive-OR function, and an OR function. The first exclusive-OR function receives two input bits from a data packet and generates a linear output value based upon exclusive disjunction between the two input bits. The OR function receives two different input bits from the data packet and generates a first nonlinear output value based upon logical disjunction between the two different input bits. The second exclusive-OR function receives the linear output value and the first nonlinear output value, and generates a second nonlinear output value based upon exclusive disjunction between the linear output value and the first nonlinear output value. In turn, the second nonlinear output value is utilized to generate a hash value for the data packet.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.