Patent · US Active

Optimization of software instruction cache by line re-ordering

US8359435B2 · kind B2 · utility

3Cited by

2References

21Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Revital Erez · Nes Ziona, IL
Brian Flachs · Austin, US
Mark Richard Nutter · Austin, US
John Kevin Patrick O'Brien · South Salem, US
Ulrich Weigand · Holzgerlingen, DE
Ayal Zaks · Mitzpe Aviv, IL

Key dates

Filing date	Dec 16, 2009
Grant date	Jan 22, 2013
Priority date	—
Expiry date	Jul 4, 2030

Classification

Technology area (CPC G)Physics
CPC primaryG06F2201/885
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A method for computing includes executing a program, including multiple cacheable lines of executable code, on a processor having a software-managed cache. A run-time cache management routine running on the processor is used to assemble a profile of inter-line jumps occurring in the software-managed cache while executing the program. Based on the profile, an optimized layout of the lines in the code is computed, and the lines of the program are re-ordered in accordance with the optimized layout while continuing to execute the program.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.