Core snoop handling during performance state and power state transitions in a distributed caching agent
US8359436B2 · kind B2 · utility
16Cited by
7References
7Claims
0Family size
Assignee
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Key dates
| Filing date | Dec 18, 2009 |
| Grant date | Jan 22, 2013 |
| Priority date | — |
| Expiry date | Jan 16, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0815
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus may provide for detecting a performance state transition in a processor core and bouncing a core snoop message on a shared interconnect ring in response to detecting the performance state transition. The core snoop message may be associated with the processor core, wherein a plurality of processor cores may be coupled to the shared interconnect ring via a distributed last level cache controller.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.