Methods and systems for debugging equivalent designs described at different design levels
US8359560B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Apr 11, 2011 |
| Grant date | Jan 22, 2013 |
| Priority date | — |
| Expiry date | May 24, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/33
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods for debugging designs are provided. First, signal correlation information for signals of a design at least two design level is obtained. Then, design descriptions corresponding to the design at the at least two design levels are loaded and presented in at least two sets of windows or at least two debugging processes which controls the respective set of windows. A selection of a first signal in a first set of windows or a first debugging process is received. In response to the selection, a second signal corresponding to the first signal is queried according to the signal correlation information, and the second signal in a second set of windows or a second debugging process is automatically selected.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.