Low etch pit density (EPD) semi-insulating III-V wafers
US8361225B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 10, 2011 |
| Grant date | Jan 29, 2013 |
| Priority date | — |
| Expiry date | Aug 10, 2031 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T428/24372
- WIPO fieldSurface technology, coating
- WIPO sectorChemistry
Abstract
Systems and methods of manufacturing wafers are disclosed using a low EPD crystal growth process and a wafer annealing process are provided resulting in III-V/GaAs wafers that provide higher device yields from the wafer. In one exemplary implementation, there is provided a method of manufacturing a group III based material with a low etch pit density (EPD). Moreover, the method includes forming polycrystalline group III based compounds, and performing vertical gradient freeze crystal growth using the polycrystalline group III based compounds. Other exemplary implementations may include controlling temperature gradient(s) during formation of the group III based crystal to provide very low etch pit density.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.