Patent · US Active

Integrated circuit package with reduced parasitic loop inductance

US8362540B2 · kind B2 · utility

1Cited by
2References
26Claims
0Family size

Assignee

Inventor

Key dates

Filing dateSep 22, 2010
Grant dateJan 29, 2013
Priority date—
Expiry dateJul 27, 2031

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH01L2924/0002
  • WIPO fieldSemiconductors
  • WIPO sectorElectrical engineering

Abstract

A multi-layer integrated circuit package includes a switched-mode power supply circuit including a plurality of transistors which form part of a main current loop of the switched-mode power supply circuit. The plurality of transistors are arranged in one or more layers of the integrated circuit package. The package further includes a conductive plate arranged in a different layer of the integrated circuit package than the plurality of transistors. The conductive plate is in close enough proximity to at least part of the main current loop so that a current can be electromagnetically induced in the conductive plate responsive to a change in current in the main current loop.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.