Recessed contact for multi-gate FET optimizing series resistance

US8362568B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Chung-Hsun Lin · White Plains, US
• Josephine B. Chang · Mahopac, US

Key dates

• Filing date: Aug 28, 2009
• Grant date: Jan 29, 2013
• Expiry date: May 19, 2031

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/021

Abstract

A transistor, which can be referred to as a multi-gate transistor or as a FinFET, includes a gate structure having a length, a width and a height. The transistor further includes at least one electrically conductive channel or fin between a source region and a drain region that passes through the width of the gate structure. The channel has a first height (h1) within the gate structure that is less than the height of the gate structure, and has a second height (h2) external to the gate structure, where h2 is less than h1. The transistor further includes a silicide layer disposed at least partially over the at least one channel external to the gate structure. Reducing the fin height external to the gate structure is shown to beneficially reduce parasitic resistance.