Integrated circuits and methods of forming the same
US8362591B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 8, 2010 |
| Grant date | Jan 29, 2013 |
| Priority date | — |
| Expiry date | Dec 2, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/64
Abstract
A three-dimensional integrated circuit includes a semiconductor substrate where the substrate has an opening extending through a first surface and a second surface of the substrate and where the first surface and the second surface are opposite surfaces of the substrate. A conductive material substantially fills the opening of the substrate to form a conductive through-substrate-via (TSV). An active circuit is disposed on the first surface of the substrate, an inductor is disposed on the second surface of the substrate and the TSV is electrically coupled to the active circuit and the inductor. The three-dimensional integrated circuit may include a varactor formed from a dielectric layer formed in the opening of the substrate such that the conductive material is disposed adjacent the dielectric layer and an impurity implanted region disposed surrounding the TSV such that the dielectric layer is formed between the impurity implanted region and the TSV.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.