Eight transistor soft error robust storage cell
US8363455B2 · kind B2 · utility
Inventors
Key dates
| Filing date | Dec 4, 2009 |
| Grant date | Jan 29, 2013 |
| Priority date | — |
| Expiry date | May 20, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/007
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A storage cell is provided with improved robustness to soft errors. The storage cell comprises complementary core storage nodes and complementary outer storage nodes. The outer storage nodes act to limit feedback between the core storage nodes and are capable of restoring the logical state of the core storage nodes in the event of a soft error. Similarly the core storage nodes act to limit feedback between the outer storage nodes with the same effect. This cell has advantages compared with other robust storage cells in that there are only two paths between the supply voltage and ground which limits the leakage power. An SRAM cell utilizing the proposed storage cell can be realized with two access transistors configured to selectively couple complementary storage nodes to a corresponding bitline. A flip-flop can be realized with a variety of transfer gates which selectively couple data into the proposed storage cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.