All-NMOS 4-transistor non-volatile memory cell

US8363469B1 · kind B1 · utility

Assignee

• NATIONAL SEMICONDUCTOR CORPORATION · US

Inventors

• Pavel Poplevine · Foster City, US
• Umer Khan · Irvine, US
• Hengyang (James) Lin · San Jose, US
• Andrew J. Franklin · Santa Clara, US

Key dates

• Filing date: Feb 2, 2010
• Grant date: Jan 29, 2013
• Expiry date: Feb 2, 2030

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B69/00

Abstract

A non-volatile memory cell includes NMOS programming, read, erase, and control transistors having gate electrodes connected to a storage node. The erase and control transistors have interconnected source, drain, and bulk electrodes. The cell is programmed by setting source, drain, bulk, and gate electrodes of all transistors to a positive voltage. An inhibiting voltage is applied to source, drain, and bulk electrodes of the read transistor, while setting source and drain electrodes of the programming transistor to the positive voltage and the bulk electrode of the programming transistor to the positive voltage or the inhibiting voltage. Source, drain, and bulk electrodes of the control transistor are then ramped to a negative control voltage while ramping source, drain, and bulk electrodes of the erase transistor to a negative erase voltage and then back to the positive voltage. Source, drain. bulk, and gate electrodes of the programming, erase, and control transistors are then returned to the positive voltage, while setting the source, drain, and bulk electrodes of the read transistor to the inhibiting voltage.