Memory device and method of controlling a write operation within a memory device

US8363484B2 · kind B2 · utility

Assignee

• Arm Limited · GB

Inventors

• Vikas Chandra · Fremont, US
• Daeyeon Kim · Ulsan, KR

Key dates

• Filing date: Mar 9, 2011
• Grant date: Jan 29, 2013
• Expiry date: Jul 28, 2031

Classification

• Technology area (CPC G): Physics
• CPC primary: G11C11/412
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A memory device and method are provided incorporating a technique for controlling a write operation within the memory device. The memory device has an array of memory cells, each memory cell supporting writing and simultaneous reading of that memory cell. Write circuitry is arranged, during a write operation, to provide write data to a number of addressed memory cells within the array, whilst word line select circuitry is responsive to the start of the write operation to assert a write word line signal that enables those addressed memory cells to store the write data. Comparing circuitry is arranged, during the write operation, to compare the write data with data currently stored in the addressed memory cells. On detecting that the write data matches the data currently stored in the addressed memory cells, the comparing circuitry asserts a control signal to the word line select circuitry to cause the word line select circuitry to de-assert the write word line signal. As a result, the pulse width of the asserted write word line signal is dependent on time taken by the addressed memory cells to store the write data, thereby leading to a significant reduction in the size of the pulse …