Methods for operating memory elements
US8363500B2 · kind B2 · utility
1Cited by
2References
25Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 13, 2011 |
| Grant date | Jan 29, 2013 |
| Priority date | — |
| Expiry date | Jun 13, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/79
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods for measuring the resistance of multiple memory elements are disclosed. The memory elements may be multi-bit memory and through precise measurement of resistance of the multi-bit memory elements, determination of how many and which memory elements fall into specific memory ranges can be accomplished. Furthermore, storage and/or display of this information may allow for the creation of resistance distribution histograms for modeling of one or more memory arrays.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.