Patent · US Active

System and method for performance modeling of integrated circuits

US8365115B2 · kind B2 · utility

23Cited by

7References

20Claims

0Family size

Assignee

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD. · TW

Inventors

Louis Liu · Baoshan, TW
Morly Hsieh · Sunnyvale, US
Dei-Pei Liu · Taipei, TW

Key dates

Filing date	Dec 3, 2009
Grant date	Jan 29, 2013
Priority date	—
Expiry date	Dec 6, 2030

Classification

Technology area (CPC G)Physics
CPC primaryG06F2119/12
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A system and method for performance modeling of integrated circuits is provided. A method for performing timing analysis on an integrated circuit is provided, the integrated circuit having a timing path. The method includes computing a number of non-common timing path elements in the timing path, assigning a timing de-rate factor to the timing path based on the number of non-common timing path elements, and computing a timing analysis on the integrated circuit using the assigned timing de-rate factor.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.