Method and system for internal layer-layer thermal enhancement
US8367478B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 2, 2011 |
| Grant date | Feb 5, 2013 |
| Priority date | — |
| Expiry date | Jul 29, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2225/06589
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The exemplary embodiments of the present invention provide a method and apparatus for enhancing the cooling of a chip stack of semiconductor chips. The method includes creating a first chip with circuitry on a first side and creating a second chip electrically and mechanically coupled to the first chip by a grid of connectors. The method further includes creating a cavity in a second side of the first chip between the connectors and filling the cavity with a thermal material. The chip stack of semiconductor chips with enhanced cooling apparatus includes a first chip with circuitry on a first side and a second chip electrically and mechanically coupled to the first chip by a grid of connectors. The apparatus further includes wherein portions of a second side of the first chip between the connectors is removed to provide a cavity in which a thermal material is placed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.