Method of manufacturing semiconductor device
US8367549B2 · kind B2 · utility
0Cited by
4References
9Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jul 28, 2010 |
| Grant date | Feb 5, 2013 |
| Priority date | — |
| Expiry date | Jul 28, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/02274
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Provided is a method of manufacturing a semiconductor device. In the method, after a thin liner is formed on a substrate on which a lower interconnection is formed, a silicon source is supplied to form a silicide layer under the liner by a reaction between the silicon source and the lower interconnection, and the silicide layer is nitrided and an etch stop layer is formed. Therefore, the lower interconnection is prevented from making contact with the silicon source, variations of the surface resistance of the lower interconnection can be prevented, and thus high-speed devices can be fabricated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.