Strained semiconductor device with recessed channel
US8368147B2 · kind B2 · utility
2Cited by
2References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 16, 2010 |
| Grant date | Feb 5, 2013 |
| Priority date | — |
| Expiry date | Oct 6, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/28518
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device having a strained channel and a method of manufacture thereof is provided. The semiconductor device has a gate electrode formed over a channel recess. A first recess and a second recess formed on opposing sides of the gate electrode are filled with a stress-inducing material. The stress-inducing material extends into an area wherein source/drain extensions overlap an edge of the gate electrode. In an embodiment, sidewalls of the channel recess and/or the first and second recesses may be along {111} facet planes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.