Multi-chip memory package with a small substrate
US8368192B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 16, 2011 |
| Grant date | Feb 5, 2013 |
| Priority date | — |
| Expiry date | Sep 16, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/1815
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed is a multi-chip memory package with a small substrate by using a die pad having an opening to substitute the chip-carrying function of a conventional substrate so that substrate dimension can be reduced. A substrate is attached under the die pad. A first chip is disposed on the substrate located inside the opening. A second chip is disposed on the die pad. An encapsulant encapsulates the top surface of the die pad, the top surface of the substrate, the first chip, and the second chip. The dimension of the substrate is smaller than the dimension of the encapsulant. In a preferred embodiment, a plurality of tie bars physically connect to the peripheries of the die pad and extend to the sidewalls of the encapsulant to have a plurality of insulated cut ends exposed from the encapsulant.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.