Integrated circuit package with segregated Tx and Rx data channels
US8368217B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 3, 2012 |
| Grant date | Feb 5, 2013 |
| Priority date | — |
| Expiry date | Jul 3, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A chip layout isolates Rx terminals and Rx ports from Tx terminals and Tx ports. Tx terminals are grouped contiguously to each other, and are segregated as a group to a given edge of the package, Rx terminals are similarly grouped and segregated to a different edge of the package. Tx and Rx data channels are disposed in a respective single layer of the package, or both are disposed in a same single layer of the package. Rx ports and Tx ports are located at an approximate center of the package, with Tx and Rx ports disposed on respective opposite sides of an axis bisecting the package. Data signals received by, and transmitted from, the chip flow in a same direction, from a first edge of the package to the center of the package and from the center of the package to a second edge of the package, respectively.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.