Memory circuit with crossover zones of reduced line width conductors
US8369135B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 3, 2010 |
| Grant date | Feb 5, 2013 |
| Priority date | — |
| Expiry date | May 18, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B61/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory circuit comprising a set of longitudinal conducting lines and a set of transverse conducting lines, wherein, each conducting line comprises alternating regions of reduced and increased line widths. The set of transverse conducting lines overlies the set of longitudinal conducting lines to define crossover zones wherein the reduced line width regions of the transverse conducting lines cross over the reduced line width regions of the longitudinal conducting lines. The circuit further comprises addressable magnetic storage elements, each disposed within a crossover zone between a longitudinal conducting line and a transverse conducting line thereof. The reduced line width regions improve magnetic flux efficiency in the magnetic storage elements and the increased line width regions lower the resistance in the conducting lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.