Pseudo dual-port SRAM and a shared memory switch using multiple memory banks and a sideband memory
US8370557B2 · kind B2 · utility
14Cited by
15References
10Claims
0Family size
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Key dates
| Filing date | Dec 19, 2008 |
| Grant date | Feb 5, 2013 |
| Priority date | — |
| Expiry date | Jun 20, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory is described which includes a main memory array made up of multiple single-ported memory banks connected by parallel read and write buses, and a sideband memory equivalent to a single dual-ported memory bank. Control logic and tags state facilitates a pattern of access to the main memory and the sideband memory such that the memory performs like a fully provisioned dual-ported memory capable of reading and writing any two arbitrary addresses on the same cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.