Methods and software for placement improvement based on global routing
US8370786B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | May 31, 2011 |
| Grant date | Feb 5, 2013 |
| Priority date | — |
| Expiry date | May 31, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and software for placing or re-placing integrated circuit cells and routing or re-routing nets between the cells in an integrated circuit layout. The method includes selecting a region of the cells in the integrated circuit layout, selecting a cell within the selected region, locating a border point where a net coupled to the selected cell crosses a border of the selected region, and moving the selected cell within the selected region to improve a timing characteristic (e.g., a wire length, capacitance, or other characteristic of the net that affects timing or delay) of the net. The method and software advantageously improve the placement of cells and routing of wires around congested or reserved regions after global routing has been performed, without causing timing violations in other signal paths on the integrated circuit device, in a computationally efficient manner.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.