Methods of fabricating semiconductor devices with sidewall conductive patterns
US8372711B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 18, 2011 |
| Grant date | Feb 12, 2013 |
| Priority date | — |
| Expiry date | May 18, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/035
Abstract
A gate pattern is disclosed that includes a semiconductor substrate, a lower conductive pattern, an upper conductive pattern, and a sidewall conductive pattern. The lower conductive pattern is on the substrate. The insulating pattern is on the lower conductive pattern. The upper conductive pattern is on the insulating pattern opposite to the lower conductive pattern. The sidewall conductive pattern is on at least a portion of sidewalls of the upper conductive pattern and the lower conductive pattern. The sidewall conductive pattern electrically connects the upper conductive pattern and the lower conductive pattern. An upper edge portion of the lower conductive pattern may be recessed relative to a lower edge portion of the lower conductive pattern to define a ledge thereon. The sidewall conductive pattern may be directly on the ledge and sidewall of the recessed upper edge portion of the lower conductive pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.