Multilayer hard mask
US8372755B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 13, 2010 |
| Grant date | Feb 12, 2013 |
| Priority date | — |
| Expiry date | May 16, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0212
Abstract
A method for fabricating a semiconductor device is disclosed. In an embodiment, the method may include providing a semiconductor substrate; forming gate material layers over the semiconductor substrate; forming a multi-layer hard mask layer over the gate material layers, wherein the multi-layer hard mask layer includes a plurality of film stacks, each film stack having a silicon oxide layer and a carbon-containing material layer, each film stack having a thickness equal to or less than about 10 angstrom; patterning the multi-layer hard mask layer, forming an opening of the multi-hard mask layer; etching the gate material layers within the opening of the multi-layer hard mask layer, forming a gate structure; performing a tilt-angle ion implantation process to the semiconductor substrate, wherein a first remaining thickness of the multi-layer hard mask layer is less than a first thickness; and thereafter performing an epitaxy growth to the semiconductor substrate, wherein a second remaining thickness of the multi-layer hard mask layer is greater than a second thickness.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.