Semiconductor memory device and production method therefor
US8373235B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 21, 2010 |
| Grant date | Feb 12, 2013 |
| Priority date | — |
| Expiry date | Oct 14, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/834
Abstract
In a static memory cell comprising six MOS transistors, the MOS transistors have a structure in which the drain, gate and source formed on the substrate are arranged in the vertical direction and the gate surrounds the columnar semiconductor layer, the substrate comprises a first active region having a first conductive type and a second active region having a second conductive type, and diffusion layers constructing the active regions are mutually connected via a silicide layer formed on the substrate surface, thereby realizing an SRAM cell with small surface area. In addition, drain diffusion layers having the same conductive type as a first well positioned on the substrate are surrounded by a first anti-leak diffusion layer and a second anti-leak diffusion layer having a conductive type different from the first well and being shallower than the first well, and thereby controlling leakage to the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.