Patent · US Active

Method and apparatus for handling an output mismatch

US8373435B2 · kind B2 · utility

8Cited by

4References

16Claims

0Family size

Assignee

Freeescale Semiconductor, Inc. · US

Inventors

Florian Bogenberger · Poing, DE
Christopher Temple · Munich, DE

Key dates

Filing date	Sep 30, 2008
Grant date	Feb 12, 2013
Priority date	—
Expiry date	Sep 30, 2028

Classification

Technology area (CPC G)Physics
CPC primaryG06F11/1675
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A system comprises a first signal processing logic module and at least one further signal processing logic module. The system further comprises mismatch handler logic module arranged to detect a mismatch between outputs of the first and at least one further signal processing logic module, the mismatch between outputs indicating a failed operation. The mismatch handler logic module further arranged, upon detection of a mismatch between outputs of the first and at least one further signal processing logic module, to analyze internal states of the first and at least one further signal processing logic module, determine whether the cause of the output mismatch is due to a transient fault, and upon determination that the cause of the output mismatch is due to a transient fault, to re-synchronize the first and at least one further signal processing logic module.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.