Dual loop phase locked loop with low voltage-controlled oscillator gain
US8373460B2 · kind B2 · utility
6Cited by
17References
7Claims
0Family size
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Key dates
| Filing date | Mar 28, 2011 |
| Grant date | Feb 12, 2013 |
| Priority date | — |
| Expiry date | Jul 14, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/089
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A dual loop PLL for generating an oscillator signal initially operates in a digital loop to achieve a frequency lock between an input reference signal and a feedback signal and then the PLL operates in an analog loop to achieve a phase lock. After attaining the phase lock, the analog loop is used to maintain the phase lock across frequency and phase variation due to changes in temperature and supply.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.