Phase interpolator and delay locked-loop circuit
US8373475B2 · kind B2 · utility
5Cited by
4References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 11, 2011 |
| Grant date | Feb 12, 2013 |
| Priority date | — |
| Expiry date | Oct 11, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0818
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A phase interpolator includes a delay difference detector and a phase interpolation driver. The delay difference detector receives a delay code to detect a delay difference. The phase interpolation driver includes two or more driver blocks complementarily operating, and the phase interpolation driver interpolate two input signals in response to the delay difference to provide an interpolated output signal. Each of two or more driver blocks includes a plurality of unit drivers, each input of the unit drivers is commonly connected, and each delay of the two or more driver blocks is varied according to the delay difference.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.