Distribution of electrostatic discharge (ESD) circuitry within an integrated circuit

US8373953B2 · kind B2 · utility

Assignee

• Freeescale Semiconductor, Inc. · US

Inventors

• Michael A. Stockinger · Austin, US
• Anthony Dunne · Cork, IE
• Alex P. Gerdemann · Austin, US
• James W. Miller · Austin, US
• Daniel O'Hare · Cork, IE
• Paul Sheridan · Neenah, US
• Jeannie Han Millaway · Panama City Beach, US

Key dates

• Filing date: Dec 29, 2008
• Grant date: Feb 12, 2013
• Expiry date: Dec 12, 2031

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/14
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Embodiments of the present disclosure provide an integrated circuit (IC) or semiconductor device. This semiconductor device includes a number of I/O pads or bumps on an outer surface of the semiconductor device, a number of electrostatic discharge (ESD) protection cells and functional modules. Individual ESD protection cells couple to and are downstream of individual I/O pads. Functional modules coupled to and are downstream of individual ESD protection cells. The ESD protection cells protect circuitry within the functional module from electrostatic discharge events. A rail clamp may provide an ESD discharge path between a first power supply bus and a second power supply bus. The ESD protection cells may be collected in groups to form clusters (with linear or irregular placement patterns). These clusters may be distributed autarchically across the semiconductor device overlapping one or more functional modules or within spaces or gaps between the functional modules.