Patent · US Active

Delay fault testing using distributed clock dividers

US8375265B1 · kind B1 · utility

5Cited by

5References

20Claims

0Family size

Assignee

TEXAS INSTRUMENTS INCORPORATED · US

Inventors

Ramakrishnan Venkatasubramanian · Plano, US
Alan Hales · Richardson, US
William Cronin Wallace · Richardson, US

Key dates

Filing date	Sep 13, 2011
Grant date	Feb 12, 2013
Priority date	—
Expiry date	Sep 26, 2031

Classification

Technology area (CPC G)Physics
CPC primaryG01R31/31858
WIPO fieldMeasurement
WIPO sectorInstruments

Abstract

In an embodiment of the invention, an integrated circuit with several clock domains bank is tested by first disabling a PLL clock and scanning test data into scan chains. Next delay fault testing (DFT) code is transmitted to each distributed clock divider on the integrated circuit. The PLL clock is then enabled to the distributed clock dividers. Selected clock dividers generate launch pulses that allow test data to be propagated from the scan chains into circuit blocks in the clock domains. Capture pulses are then generated by selected distributed clock dividers to capture test data coming form the circuit blocks into the scan chains. Next the PLL clock is disabled and the test data is scanned from the scan chains to an on-chip test control circuit.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.