Methods for reduced test case generation
US8375350B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 21, 2011 |
| Grant date | Feb 12, 2013 |
| Priority date | — |
| Expiry date | Nov 21, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/327
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment of the invention, a method is disclosed including executing one or more commands of a work script to perform work on a portion of a netlist of an integrated circuit design; receiving an indication of a program fault in a first integrated circuit (IC) design program performing work on the portion of the netlist in response to the one or more commands of the work script; and generating a debug work script associated with the work script in response to the program fault, the debug work script including an identification of the portion of the netlist of the integrated circuit design upon which work was being performed during the program fault.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.