CMOS integration method for optimal IO transistor VT

US8377772B2 · kind B2 · utility

Assignee

• TEXAS INSTRUMENTS INCORPORATED · US

Inventors

• Weize Xiong · Austin, US
• Greg Baldwin · Plano, US

Key dates

• Filing date: Aug 17, 2010
• Grant date: Feb 19, 2013
• Expiry date: Mar 4, 2031

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/0191

Abstract

Various embodiments provide methods for fabricating dual supply voltage CMOS devices with a desired I/O transistor threshold voltage. The dual supply voltage CMOS devices can be fabricated in a semiconductor substrate that includes isolated regions for a logic NMOS transistor, a logic PMOS transistor, an I/O NMOS transistor, and an I/O PMOS transistor. Specifically, the fabrication can first set and/or adjust the threshold voltage (VT) of each of the I/O NMOS transistor and the I/O PMOS transistor to a desired level. Logic NMOS and logic PMOS transistors can then be formed with I/O NMOS and I/O PMOS transistors masked without affecting the set/adjusted VT of the I/O transistors.