Semiconductor storage device
US8378425B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 3, 2010 |
| Grant date | Feb 19, 2013 |
| Priority date | — |
| Expiry date | Nov 6, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6728
Abstract
It is intended to achieve a sufficiently-small SRAM cell area and a stable operation margin in a CMOS 6T-SRAM comprising a vertical transistor SGT. In a static type memory cell made up using six MOS transistors, each of the MOS transistor constituting the memory cell is formed on a planar silicon layer formed on a buried oxide film, to have a structure where a drain, a gate and a source are arranged in a vertical direction, wherein the gate is formed to surround a pillar-shaped semiconductor layer. The planar silicon layer comprises a first active region having a first conductive type, and a second active region having a second conductive type. The first and second active regions are connected to each other through a silicide layer formed in a surface of the planar silicon layer to achieve an SRAM cell having a sufficiently-small area.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.