Patent · US Active

Dummy wafers in 3DIC package assemblies

US8378480B2 · kind B2 · utility

44Cited by

57References

11Claims

0Family size

Assignee

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD. · TW

Inventors

Ming-Fa Chen · Taichung, TW
Chia-Yen Lee · Taoyuan, TW

Key dates

Filing date	Mar 4, 2010
Grant date	Feb 19, 2013
Priority date	—
Expiry date	May 1, 2030

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/181
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A package structure includes a first die, and a second die over and bonded to the first die. The second die has a size smaller than a size of the first die. A dummy chip is over and bonded onto the first die. The dummy chip includes a portion encircling the second die. The dummy chip includes a material selected from the group consisting essentially of silicon and a metal.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.