Combined write assist and retain-till-accessed memory array bias
US8379465B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 21, 2010 |
| Grant date | Feb 19, 2013 |
| Priority date | — |
| Expiry date | Jan 2, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/413
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Bias circuitry for a static random-access memory (SRAM) with a retain-till-accessed (RTA) mode and with write assist bias in a normal operating mode. The memory is constructed of multiple memory array blocks of SRAM cells. Bias devices are associated with each memory array block, and associated with one or more columns. Each bias device includes a diode-connected transistor in parallel with a shorting transistor, between a power supply voltage and a power supply bias node for cells in its column or columns. The shorting transistor receives control signals from control logic so that the diode-connected transistor for each column is shorted during read cycles, and in write cycles in which its columns are not selected; in write cycles in which its columns are selected, the shorting transistor in the bias device is turned off, so that a reduced power supply voltage is applied to the selected column. The shorting transistors for all columns in the block are turned off in the RTA mode. An additional transistor in series with the diode-connected transistor may be included, to enable a floating power supply bias mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.