Patent · US Active

Structure and methods for measuring margins in an SRAM bit

US8379467B2 · kind B2 · utility

5Cited by

0References

5Claims

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Assignee

TEXAS INSTRUMENTS INCORPORATED · US

Inventors

Xiaowei Deng · Plano, US
Theodore W. Houston · Richardson, US
Wah Kit Loh · Richardson, US

Key dates

Filing date	Mar 8, 2011
Grant date	Feb 19, 2013
Priority date	—
Expiry date	Mar 8, 2031

Classification

Technology area (CPC G)Physics
CPC primaryG11C2029/5002
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Integrated circuit for performing test operation of static RAM bit and for measuring the read margin, write margin, and stability margin of SRAM bits with operational circuitry that includes effects of the SRAM array architecture and circuit design. In addition, the integrated circuit has a built-in self-test circuit for measuring the read margin, write margin, and stability margin of SRAM that excludes the effects of SRAM array architecture and circuit design.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.