Atomic memory operation cache protocol with opportunistic combining
US8380935B2 · kind B2 · utility
2Cited by
3References
20Claims
0Family size
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Key dates
| Filing date | Jun 12, 2009 |
| Grant date | Feb 19, 2013 |
| Priority date | — |
| Expiry date | Jun 30, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0815
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An atomic memory operation cache comprises a cache memory operable to cache atomic memory operation data, a write timer, and a cache controller. The cache controller is operable to update main memory with one or more dirty atomic memory operation cache entries stored in the cache memory upon expiration of the write timer, and is further operable to update main memory with one or more dirty atomic memory operation cache entries stored in the cache memory upon eviction of the one or more dirty atomic memory operation cache entries from the cache memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.