Apparatus and method for testing shadow logic
US8381049B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Jun 14, 2010 |
| Grant date | Feb 19, 2013 |
| Priority date | — |
| Expiry date | May 4, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/12015
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system for testing faults in shadow logic includes a sequential block coupled to a shadow logic block and a delaying block to receive test patterns for testing the shadow logic block. The delaying block delays the test patterns by an access time of the sequential block to generate delayed test patterns. The delayed test patterns are passed to the shadow logic block for testing faults.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.