Method and apparatus for increased effectiveness of delay and transition fault testing

US8381050B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Pamela S. Gillis · Jericho, US
• Jack R. Smith · Burlington, US
• Tad J. Wilder · South Hero, US
• Francis Woytowich · Vergennes, US
• Tian Xia · Shanghai, CN

Key dates

• Filing date: Nov 25, 2009
• Grant date: Feb 19, 2013
• Expiry date: Jul 18, 2031

Classification

• Technology area (CPC G): Physics
• CPC primary: G01R31/318594
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

The invention disclosed herein provides increased effectiveness of delay and transition fault testing. The method of delay fault testing integrated circuits comprises the steps of creating a plurality of test clock gating groups. The plurality of test clock gating groups comprising elements defining inter-element signal paths within the integrated circuit. Each of the elements of the plurality of test clock gating groups share clock frequency and additional shared characteristics. At least one test signal is commonly and selectively connected through at least one low-speed gate transistor to each of the elements comprising each of the plurality of test clock gating groups based on membership in the test clock gating group. This invention can also be practiced using scan-enable gating groups for the same purposes.