Using a timing exception to postpone retiming
US8381142B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 9, 2007 |
| Grant date | Feb 19, 2013 |
| Priority date | — |
| Expiry date | Oct 13, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for designing a system on a target device is described. In one embodiment of the method, a plurality of registers is replaced with at least one register and a timing exception. In one embodiment, the registers in the plurality of registers are in series or substantially in series. In one embodiment, the timing exception is a multi-cycle exception. In one embodiment, the method also includes identifying a critical combinational logic path that is followed or preceded by the plurality of registers. Further, in one aspect, the timing exception is removed and registers are inserted into the critical combinational logic path to account for the removed timing exception. In one embodiment, a network flow algorithm is performed to determine the locations for inserting registers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.