Method of adapting a layout of a standard cell of an integrated circuit
US8381162B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 5, 2010 |
| Grant date | Feb 19, 2013 |
| Priority date | — |
| Expiry date | Mar 16, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/39
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of adapting a layout of a standard cell of an integrated circuit is provided. A current collection path in the standard cell is selected which connects components within the standard cell to an output connection, wherein the current collection path is arranged to collect current from the components at a plurality of current collection points arranged along its length. A maximum current location on the current collection path is determined at which a maximum possible current flow in the current collection path will occur if the output connection is connected there, the maximum possible current flow being a sum of current contributions from the current collection points. A maximum width of the current collection path at the maximum current location is determined such that the maximum width satisfies a minimum path width requirement with respect to the maximum possible current flow. Then a local width of the current collection path at a selected distance from the maximum current location is determined, the local width being less than or equal to the maximum width, such that the local width satisfies the minimum path width requirement with respect to a maximum local current th…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.