CMOS compatible pressure sensor for low pressures
US8381596B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 17, 2010 |
| Grant date | Feb 26, 2013 |
| Priority date | — |
| Expiry date | Jan 6, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01L9/0054
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Pressure sensors having a topside boss and a cavity formed using deep reactive-ion etching (DRIE) or plasma etching. Since the boss is formed on the topside, the boss is aligned to other features on the topside of the pressure sensor, such as a Wheatstone bridge or other circuit elements. Also, since the boss is formed as part of the diaphragm, the boss has a reduced mass and is less susceptible to the effects of gravity and acceleration. These pressure sensors may also have a cavity formed using a DRIE or plasma etch. Use of these etches result in a cavity having edges that are substantially orthogonal to the diaphragm, such that pressure sensor die area is reduced. The use of these etches also permits the use of p-doped wafers, which are compatible with conventional CMOS technologies.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.