Integrated high-K/metal gate in CMOS process flow
US8383502B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 20, 2011 |
| Grant date | Feb 26, 2013 |
| Priority date | — |
| Expiry date | Jul 20, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/856
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating a semiconductor device includes providing a semiconductor substrate having a first active region and a second active region, forming a first metal layer over a high-k dielectric layer, removing at least a portion of the first metal layer in the second active region, forming a second metal layer on first metal layer in the first active region and over the high-k dielectric layer in the second active region, and thereafter, forming a silicon layer over the second metal layer. The method further includes removing the silicon layer from the first gate stack thereby forming a first trench and from the second gate stack thereby forming a second trench, and forming a third metal layer over the second metal layer in the first trench and over the second metal layer in the second trench.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.