Gate-all-around nanowire field effect transistors
US8384065B2 · kind B2 · utility
32Cited by
44References
35Claims
0Family size
Assignee
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Key dates
| Filing date | Dec 4, 2009 |
| Grant date | Feb 26, 2013 |
| Priority date | — |
| Expiry date | Jun 15, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/215
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
A method for forming a nanowire field effect transistor (FET) device, the method includes forming a suspended nanowire over a semiconductor substrate, forming a gate structure around a portion of the nanowire, forming a protective spacer adjacent to sidewalls of the gate and around portions of nanowire extending from the gate, removing exposed portions of the nanowire left unprotected by the spacer structure, and epitaxially growing a doped semiconductor material on exposed cross sections of the nanowire to form a source region and a drain region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.