Method and apparatus for gating a clock signal
US8384437B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 15, 2008 |
| Grant date | Feb 26, 2013 |
| Priority date | — |
| Expiry date | Sep 15, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0016
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A semiconductor device comprising clock gating logic. The clock gating logic comprises clock freezing logic arranged to receive a selected clock signal and an enable signal. The clock freezing logic is further arranged to output a gated clock signal substantially corresponding to the selected clock signal when the enable signal comprises an inactive state, and to freeze the output gated clock signal when the enable signal comprises an active state. The clock gating logic further comprises polarity comparison logic arranged to compare polarities of an input clock signal and the gated clock signal and selector logic arranged to select from the input clock signal and an inverted input clock signal, based on a result of a comparison of the polarities of the input clock signal and the gated clock signal and to provide the selected clock signal to the clock freezing logic. The polarity comparison logic and the selector logic being further arranged such that, upon the enable signal transitioning from an active state to an inactive state, the selected clock signal provided to the clock freezing logic comprises a polarity substantially equivalent to that of the gated clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.