Apparatus for clock skew compensation
US8384455B2 · kind B2 · utility
1Cited by
11References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 23, 2011 |
| Grant date | Feb 26, 2013 |
| Priority date | — |
| Expiry date | Sep 16, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/12
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An apparatus for clock skew compensation is provided. The apparatus includes a first delay locked loop (DLL) module disposed in a first die and a second DLL module disposed in a second die. A first input terminal of the first DLL module receives a reference clock. A first input terminal of the second DLL module is electrically connected to an output terminal of the first DLL module. An output terminal of the second DLL module is electrically connected to a second input terminal of the first DLL module.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.