Patent · US Active

Circuit for and method of reducing power consumption in input ports of an integrated circuit

US8384472B2 · kind B2 · utility

1Cited by
8References
20Claims
0Family size

Assignee

Inventors

Key dates

Filing dateJan 28, 2009
Grant dateFeb 26, 2013
Priority date
Expiry dateFeb 24, 2029

Classification

  • Technology area (CPC G)Physics
  • CPC primaryG11C5/147
  • WIPO fieldComputer technology
  • WIPO sectorElectrical engineering

Abstract

A circuit for reducing power consumption in input ports of an integrated circuit is disclosed. The circuit comprises a plurality of receiver circuits of the integrated circuit for receiving input signals coupled to the integrated circuit; and a bias current generator coupled to the plurality of receiver circuits, the bias current generator providing a bias voltage for each receiver circuit of the plurality of receiver circuits to mirror the current in the bias current generator in each of the receiver circuits. A method of reducing power consumption in input ports of an integrated circuit is also disclosed.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.