Patent · US Active

Memory controller

US8386702B2 · kind B2 · utility

1Cited by

1References

23Claims

0Family size

Assignee

HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. · US

Inventors

Larry J. Thayer · Fort Collins, US
Leith L. Johnson · Fort Collins, US

Key dates

Filing date	Oct 27, 2005
Grant date	Feb 26, 2013
Priority date	—
Expiry date	Nov 4, 2030

Classification

Technology area (CPC G)Physics
CPC primaryG06F12/0866
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

In one embodiment, a memory control system is provided with a memory controller having 1) a first interface to receive memory read/write requests; 2) a second interface to read/write data from a number of memory modules; 3) a memory cache containing spare memory locations; and 4) logic to, upon receipt of a memory read/write request, i) direct the read/write request to the memory cache when an address associated with the read/write request resides in the memory cache, and ii) direct the read/write request to the second interface when the address associated with the read/write request does not reside in the memory cache.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.