Memory devices and systems including write leveling operations and methods of performing write leveling operations in memory devices and systems
US8386737B2 · kind B2 · utility
18Cited by
4References
33Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 15, 2009 |
| Grant date | Feb 26, 2013 |
| Priority date | — |
| Expiry date | Oct 21, 2031 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device controller having a write leveling mode of operation comprises: a clock generator that generates a periodic clock signal for transmission to a memory device; a data strobe generator that generates a data strobe signal for transmission to the memory device; and a control unit that generates command signals for transmission to the memory device, the controller, during operation in the write leveling mode, generating a command signal and a write leveling control signal for transmission to the memory device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.