Processor and method for dynamic and selective alteration of address translation
US8386747B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 11, 2009 |
| Grant date | Feb 26, 2013 |
| Priority date | — |
| Expiry date | Oct 4, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0284
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Non-intrusive techniques have been developed to dynamically and selectively alter address translations performed by, or for, a processor. For example, in some embodiments, a memory management unit is configured to map from effective addresses in respective effective (or virtual) address spaces to physical addresses in the memory, wherein the mappings performed by the memory management unit are based on address translation entries of an address translation table. For a subset of less than all processes, entry selection logic selects from amongst plural alternative mappings coded in respective ones of the address translation entries. For at least some effective addresses mapped for a particular process of the subset, selection of a particular address translation entry is based on an externally sourced value. In some embodiments, only a subset of effective addresses mapped for the particular process are subject to dynamic runtime alteration of the address translation entry selection.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.