Circuit for estimating latency through a FIFO buffer
US8386828B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 16, 2010 |
| Grant date | Feb 26, 2013 |
| Priority date | — |
| Expiry date | May 21, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/096
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Circuits and methods are provided for estimating a latency through a FIFO buffer. A first detector detects first instances of a pattern in first data values serially written to a write port of the FIFO buffer. A second detector detects second instances of the pattern in second data values serially read from a read port of the FIFO buffer. The second data values are the first data values delayed by the latency through the FIFO buffer. A counter counts a count of active transitions of a sample clock signal. The counter starts on each detected first instance and stops on each detected second instances. The count provides an estimate of the latency of the FIFO buffer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.